The present invention relates to memory accessing and addressing for a parallel processing computer system. More particularly, the invention relates to a distributed/shared memory in which each of the processors constituting a parallel processing computer system can refer to all of the memories.
The demand for a high-speed processing performance of computers has prompted the appearance of a parallel processing computer system in which plural arithmetic processors are linked to each other. A TCMP (Tightly Coupled Multi-Processor) type parallel processing computer system has several arithmetic processors, which share one memory.
On the other hand, there has appeared a parallel processing computer system having many more arithmetic processors than those of the TCMP type, more specifically, several hundreds to several thousands of arithmetic processors. From the viewpoint of the degree of ease in realizing the hardware, each arithmetic processor has its own memory independently and the arithmetic processors do not share one storage, which is a parallel processing computer system of distributed memory type.
The distributed memory type can have a higher performance than the TCMP type. However, it has been pointed out that the distributed memory type parallel processor computer system involves some problems in portability being restricted by a conventional programming style (in which a single arithmetic processor and a single memory is assumed to be used) and in the case of programming generally. Therefore, in recent years, a distributed/shared memory type parallel processing computer system tends to be introduced increasingly in which each of the arithmetic processors of a distributed memory type can refer to the memories of the other arithmetic processors.
In order to implement a distributed/shared memory type, various problems should be solved. One of them is how to allow each of the processors to refer to the memories of the other processors. This problem can be solved by addressing. More specifically, in the address space of each processor, the memories of the other processors are mapped. For example, "RP3 Processor-Memory Element", p. 782 to p. 789, a proceeding on the International Conference on Parallel Processing in 1985 and U.S. Pat. No. 4,754,394 use an address having a format as shown in FIG. 4 to refer to the memory of the other arithmetic processors. Japanese Patent Laid-Open No. 155465/1981 uses an address having a type shown in FIG. 11.
The address shown in FIG. 4 is such that the accessed arithmetic processor having a memory to be referred to is designated by the fixed length processor number field 401, and the address in the memory is designated by the fixed length offset field 402. Also, the address shown in FIG. 11 is such that whether the memory to be referred to belongs to the accessing processor or to another processor is designated by one bit field F 1101; the accessed arithmetic processor having the memory to be referred to when accessing another processor is designated by the fixed length processor number field 1102; the address in the memory is designated by the fixed length offset field 1103; and the content of the fields 1102 and 1103 coupled to each other is used as the address when accessing the memory of the accessing processor.